module RTC_clock(clk50m,reset,cp,HEX2,HEX3,HEX4,HEX5, HEX6,HEX7,DATA);
	input clk50m,reset,cp;
	input [15:0]DATA;
	output [0:6]HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;
	reg [25:0]cnt;
	reg [11:0]clk1;
	wire [3:0]clk1_out,clk2_out,clk3_out,clk4_out,clk2,clk3,clk4,clk5;
	wire [3:0]ad5,ad4,ad3,ad2,ad1,ad0;
	/*分频模块*/
	always @(posedge clk50m or negedge reset)begin
		if(!reset) begin
			cnt<=0; end
		else if(cnt==26'd50000000) 
			begin cnt<=0;clk1<=~clk1;end
		else 
			cnt<=cnt+1;
	end

	clock_1 u1(clk1,clk1_out,ad0,reset);
	assign clk2 = clk1_out;
	clock_2 t1(clk2,clk2_out,ad1,reset);
	assign clk3 = clk2_out;
	clock_1 u2(clk3,clk3_out,ad2,reset,cp,DATA[3:0]);
	assign clk4 = clk3_out;
	clock_2 t2(clk4,clk4_out,ad3,reset,cp,DATA[7:4]);
	assign clk5 = clk4_out;
	clock_3 o1(clk5,ad4,ad5,reset,cp,DATA[15:8]);

	show_decode4_7 q1(ad0,HEX2);
	show_decode4_7 q2(ad1,HEX3);
	show_decode4_7 q3(ad2,HEX4);
	show_decode4_7 q4(ad3,HEX5);
	show_decode4_7 q5(ad4,HEX6);
	show_decode4_7 q6(ad5,HEX7);
endmodule

//模块1
module clock_1(clk_in,clk_out,clk_cnt,rst,load,ST);
	input  clk_in,rst,load;
	input [3:0]ST;
	output reg[3:0]clk_cnt,clk_out;
	always@(posedge clk_in or negedge rst or posedge load) begin
		if(!rst) begin
			clk_cnt<=0;end
		else if(load) 
			begin clk_cnt<=ST;end
		else if(clk_cnt==4'd9)
			begin clk_cnt <= 0; clk_out <= 1'b1; end
		else 
			begin clk_cnt <= clk_cnt+1; clk_out <= 1'b0; end
	end
endmodule

//模块2
module clock_2(clk_in,clk_out,clk_cnt1,rst,load,ST);
	input clk_in,rst,load;
	input [3:0]ST;
	output reg[3:0]clk_cnt1, clk_out;
	always@(posedge clk_in or negedge rst or posedge load) begin
		if(!rst) begin
			clk_cnt1<=0;end
		else if(load)
			begin clk_cnt1<=ST;end
		else if(clk_cnt1==4'd5) 
			begin clk_cnt1 <= 0; clk_out <= 1'b1; end
		else
			begin clk_cnt1 <= clk_cnt1+1; clk_out <= 1'b0; end
	end
endmodule

//模块3
module clock_3(clk_in,units,tens,rst,load,ST);
	input clk_in,rst,load;
	input [7:0]ST;
	output reg[3:0]units,tens;
	wire [3:0]ap1,ap2;
	assign {ap2,ap1}=ST;
	always@(posedge clk_in or negedge rst or posedge load) begin
		if(!rst) begin
			units<=0;
			tens<=0;end
		else if(load)
			begin units <= ap1;tens <= ap2;end
		else if(tens==4'd2 &&units==4'd3) 
			begin tens <= 4'd0; units <= 4'd0; end
		else if(tens!=4'd2&&units==4'd9)
			begin tens <= tens+4'd1; units <= 4'd0; end
		else
			units<=units+1;
	end
endmodule

//显示模块
module show_decode4_7(ST,HEX);
	input [3:0]ST;
	output reg[0:6] HEX;

	always @(*) begin
		case(ST)
			4'b0000: HEX=~7'b1111110;
			4'b0001: HEX=~7'b0110000;
			4'b0010: HEX=~7'b1101101;
			4'b0011: HEX=~7'b1111001;
			4'b0100: HEX=~7'b0110011;
			4'b0101: HEX=~7'b1011011;
			4'b0110: HEX=~7'b1011111;
			4'b0111: HEX=~7'b1110000;
			4'b1000: HEX=~7'b1111111;
			4'b1001: HEX=~7'b1111011;
			default: HEX=~7'b0000000;
		endcase
	end
endmodule